The present invention relates to a non-volatile semiconductor memory in which a threshold value of a transistor is changed by holding charges in an insulating film in the gate structure.
Conventionally, such a non-volatile semiconductor memory, for example, an M O N O S (Metal-Oxide-Nitride-Oxide-Semiconductor) element has been known. The structure of the memory will be explained below the reference to FIG. 5. The M O N O S element shown in FIG. 5 includes a gate structure in which a tunnelling oxide film 2 of a thin silicon oxide film, a silicon nitride film 3 hereinafter referred to as merely nitride film, a silicon oxide film 4 hereinafter referred to as a top oxide film and a gate electrode 5 which is conducting layer of an N.sup.+ polysilicon layer, etc., are stacked in that order on a P type silicon substrate 1.
The writing of data in M O N O S element is carried out as follows. When a source S is grounded and a positive voltage is applied to the gate G and the drain D (voltage to the gate G is a little higher than to the drain D), respectively, a large electric field is generated near the drain diffusion layer 7. Consequently, electrons in the channel region are accelerated and a charge consisting of a number of electrons (hot electrons) having a high energy is generated. A part of the hot electron charge is drawn into the drain diffusion layer 7. Nevertheless, another part thereof is drawn into the nitride film 3 by tunnelling through the oxide film 2 and is locally held in the nitride film 3, which results in a state in which a threshold value is increased, namely, a state in which data are written is obtained.
The erasing of data from the M O N O S element is carried out as follows. When the source S is grounded, a negative voltage is applied to the gate G and a positive voltage is applied to the drain D, respectively, so that the bending of the energy band becomes large just below the gate on the surface of the drain diffusion layer 7, namely, and the tunnelling effect between bands is generated and holes (avalanche hot holes) are generated. A part of the charge of generated holes becomes a substrate current. Nevertheless, another part thereof is accelerated by the electric field just below the gate to be injected into the nitride film 3. Consequently, the negative charge held in the nitride film 3 is cancelled and the threshold value is reduced. In turn, a number of holes are generally injected into the nitride film 3 to provide a larger charge than the writing negative charge so that a so-called over erase state is generated. However, the residual charge of holes in the nitride film 3 is locally held at the drain side of the nitride film 3. Thus, the channel conduction between the source S and the drain D does not occur.
Reading of data from the M O N O S element is carried out by grounding the source S and applying a lower positive voltage to the gate G and the drain D than in the writing of the data. In this case, the voltage applied to the gate G is at a higher level. When the data is written, the channel from the source different layer 6 does not reach the drain diffusion layer 7 because of the influence of the negative charge held in the nitride film 3. Therefore, a state in which current does not flow between the source S and the drain D (a state in which the threshold value is increased) is obtained. Namely, 1 can be read. In a case where data is not written (erase), a state in which a channel is formed between the source diffusion layer 6 and the drain diffusion layer 7 and current flows (a state in which the threshold value is reduced) is obtained. Namely, O can be read.
Conventional memory devices having such structure, however, have the following problems.
The conventional problems will be explained with reference to FIG. 6. FIG. 6 is a diagram of a memory device in which the M O N O S elements of the type shown in FIG. 5 are connected in a matrix. In FIG. 6, n and n-1 are word lines connected to the gate G of each element, m-1, m, and m+1 are bit lines connected to the drain D of each element. The source S of each element is grounded. When the word line n and the bit line m are held at a high voltage level to write data into the element M1, negative charges are stored in the nitride film in the gate dielectric of the element M1 as mentioned above.
On the other hand, since in the element M2, a low level voltage is applied to the gate G and the high level voltage is applied to the drain D, a comparatively large electric field is generated near the drain and negative charges stored in the nitride film 3 are drawn into the drain or, on the contrary, a state in which the written data is disturbed (drain wring disturbance) is sometimes generated by the fact that the holes generated near the drain are injected into the nitride film 3.
Further, in the elements M3 and M4, since the high level voltage is applied to the gate G, a state in which negative charges stored in the nitride film 3 are drawn into the word line n through the gate electrode 5 (gate writing disturbance) is sometimes generated in the element M3 and in turn, an error writing problem may be generated in the element M4 because negative charges in the channel region are injected into the nitride film 3.
Additionally, when the channel length becomes short by miniaturization of the element and a high level voltage is applied to the drain D, the depletion layer extending from the drain diffusion layer 7 reaches the source diffusion layer 6. Thus, the punch through current is increased and a reading error may be generated.